STT-MRAM technology for writing of memory bits was described by C. Slonczewski in “Current driven excitation of magnetic multilayers”, J. Magn. Magn. Mater. V 159, L1-L7 (1996), and is highly competitive with existing semiconductor memory technologies such as SRAM, DRAM, and flash. STT-MRAM has a MTJ cell based on a tunneling magnetoresistance (TMR) effect wherein a MTJ stack of layers has a configuration in which two ferromagnetic layers are separated by a thin insulating tunnel barrier layer. One of the ferromagnetic layers called the pinned layer has a magnetic moment that is fixed in a perpendicular-to-plane direction. The second ferromagnetic layer (free layer) has a magnetization direction that is free to rotate between a direction parallel to that of the pinned layer (P state) and an antiparallel direction (AP state). The difference in resistance between the P state (Rp) and AP state (Rap) is characterized by the equation (Rap-Rp)/Rp that is also known as DRR. It is important for MTJ devices to have a large DRR value, preferably higher than 1, as DRR is directly related to the read margin for the memory bit, or how easy it is to differentiate between the P state and AP state (0 or 1 bits).
State of the art STT-MRAM structures preferably have a free layer with high PMA to allow data retention at small device sizes. For functional MRAM and STT-MRAM products, the free layer (information storage layer) must have a high enough energy barrier (Eb) to resist switching due to thermal and magnetic environmental fluctuations. The value Δ=kV/kBT is a measure of the thermal stability of the magnetic element where kV is also known as Eb between the two magnetic states (P and AP), kB is the Boltzmann constant, and T is the temperature. This energy barrier to random switching is related to the strength of the perpendicular magnetic anisotropy (PMA) of the free layer. One practical way to obtain strong PMA is through interfacial PMA at an interface between an iron rich free layer and a MgO tunnel barrier layer. This combination enables good lattice matching as well as the possibility to use MgO as a spin filtering element thereby providing a read signal for the device. Since the writing current density and voltage across the device is significant, this spin filtering element must have high structural quality to sustain billions of write cycles during the lifetime of the memory device.
Recent free layer designs have incorporated a second free layer/metal oxide interface on an opposite side of the free layer with respect to the tunnel barrier to achieve even higher PMA due to an additional interfacial PMA contribution. Therefore, total PMA in the free layer is enhanced with a MgO/CoFeB free layer/MgO stack, for example, that also increases Eb and thermal stability. The spin filtering capability of the second metal oxide layer that is also referred to as a Hk enhancing layer is typically not used. Because the second metal oxide layer contributes to the total resistance of the device without affecting the read signal, it is engineered to have as low resistance as possible.
Equation (1) shows the effect of the second metal oxide (mox) layer resistance contribution to total MTJ resistance while Equation (2) indicates a negative impact (reduction) for DRR.
                              DRR          =                                                                                          R                    AP                                    -                                      R                    P                                                                    R                  P                                            ⁢                                                          ⁢              where              ⁢                                                          ⁢                              R                AP                                      =                                                            R                  AP                  barrier                                +                                                      R                    AP                    mox                                    ⁢                                                                          ⁢                  and                  ⁢                                                                          ⁢                                      R                    P                                                              =                                                R                  P                  barrier                                +                                  R                  P                  mox                                                                    ⁢                                  ⁢                              Since            ⁢                                                  ⁢                          R              AP              mox                                =                      R            P            mox                                              Eq        .                                  ⁢                  (          1          )                                        DRR        =                                                            R                AP                barrier                            +                              R                AP                mox                            -                              (                                                      R                    P                    barrier                                    +                                      R                    P                    mox                                                  )                                                                    R                P                barrier                            +                              R                P                mox                                              =                                                    R                AP                barrier                            -                              R                P                barrier                                                                    R                P                barrier                            +                              R                P                mox                                                                        Eq        .                                  ⁢                  (          2          )                    
In summary, the series resistance caused by the second metal oxide layer (RAPmox and RTPmox) will cause a reduction in DRR, effectively reducing the STT-MRAM (or MRAM) bit reading margin, as well as increasing the bit's writing voltage by adding a series resistance. Since a MgO Hk enhancing layer or the like is required to achieve strong PMA for enhanced thermal stability, an improved second metal oxide layer structure is needed such that high interfacial PMA is maintained at the free layer interface while significantly reducing the series resistance contribution from the second metal oxide layer.
Generally, low resistance in a Hk enhancing layer is achieved through a lower (non-stoichiometric) oxidation state, or thinning a fully oxidized layer. However, the latter is difficult to accomplish without oxidizing a portion of the free layer. Unfortunately, with regard to a non-stoichiometric oxidation state, oxygen vacancies in the metal oxide layer decrease the thermal stability for the device, and allow for increased mobility of oxygen within the layer, and greater diffusion of metal atoms such as Ta from adjacent layers. Since STT-MRAM devices are likely to be integrated in standard Complementary Metal Oxide Semiconductor (CMOS) processes comprising 400° C. anneal cycles totaling up to 5 hours, this high temperature combined with highly mobile oxygen in a MgO Hk enhancing layer often results in a loss of interfacial PMA at the free layer/Hk enhancing layer interface, and degraded free layer properties. Thus, an improved Hk enhancing layer design must also provide a means of minimizing oxygen diffusion and metal diffusion through the layer in order to preserve high PMA in the free layer and device thermal stability up to 400° C.